1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit devices and level conversion circuits, and more particularly, to semiconductor integrated circuit devices in which a plurality of circuit units driven by a plurality of different power supply voltages are formed on a single substrate, and to level conversion circuits used in the semiconductor integrated circuit devices.
2. Description of the Related Art
The trend in manufacturing semiconductor integrated circuit devices (such as large-scale integrated circuit devices) is to use lower power supply voltages to reduce power consumption. Recent integrated circuit devices are driven by 1.2 V power supplies, even though input/output units (I/O units), the interfaces with circuits driven by an external 3.3 V power supply, are also driven by a 3.3 V power supply.
Additionally, a single semiconductor chip may have two or more circuit blocks that are driven by different respective supply voltages. Such circuit blocks require level conversion circuits for raising or lowering voltage levels between circuit blocks having different respective supply voltages. FIG. 1(a) schematically illustrates a circuit diagram of a conventional level-down circuit (a circuit for converting a large-amplitude signal output by a circuit block operating on a 3.3 V power supply, for example, into a small-amplitude signal for input to a circuit block operating on a 1.2 V power supply, for example), and FIG. 2(a) schematically illustrates a conventional level-up circuit (a circuit for converting a small-amplitude signal output by a circuit block operating on a 1.2 V power supply, for example, into a large-amplitude signal for input to a circuit block operating on a 3.3 V power supply, for example).
In FIG. 1(a), VDDQ represents a 3.3 V input, VDD is a 1.2 V power supply, and VSS a reference, or ground, potential. Thus, VDDQ is a large-amplitude signal, and the output is a small-amplitude signal based upon the VDD potential.
In FIG. 1(a), a P-type MOS (PMOS) transistor 200 and an N-type MOS (NMOS) transistor 201 are shown, connected to receive on their respective gates an input INO having an amplitude of 0.0 V when low and 3.3 V when high, for example. INO is thus considered to be a large-amplitude signal input. The circuit shown in FIG. 1(a) outputs a small-amplitude signal out0 having an output value of 1.2 V, for example, based upon the power supply VDD. FIG. 1(b) illustrates the respective waveforms of IN0 and out0.
Since, in the PMOS transistor 200 and NMOS transistor 201, a maximum voltage of 3.3 V may be applied between gate and source, PMOS transistor 200 and NMOS transistor 201 are formed with a thick gate oxide layer.
In FIG. 2(a), the level-up circuit is constituted by PMOS transistors 202, 203 and NMOS transistors 204, 205. Small-amplitude input signals in0 and in0b are coplementary dual rail signals. Output signal OUT0 is a large-amplitude output signal of, for example, 3.3 V, based upon power supply VDDQ. MOS transistors 202-205 each have a thick gate oxide layer similar to that of the MOS transistors 200, 201 of FIG. 1(a). FIG. 2(b) illustrates the respective waveforms of input signals in0, in0b and output signal OUT0.
In a conventional level-down circuit such as that shown in FIG. 1(a), the logic threshold is typically VDD/2, or close to 0.6 V. Large-amplitude input signals, because their amplitudes are relatively large, generally tend to produce noise of a type such that the ground level fluctuates. When the ground level fluctuates more than 0.6 V, the signal is judged erroneously to be a high level in the circuit of FIG. 1(a), resulting in a low-level output at out0. Hence, in the conventional level-down circuit, as the VDD supply decreases in voltage, the logic threshold becomes lower, and an incorrect logic value may be produced at the output out0 in the presence of even very small noise.
In the level-up circuit of FIG. 2(a), when the VDDQ power supply is on but the input power VDD is off, the values of in0 and in0b are undefined, causing a through-current to flow between VDDQ and VSS. Hence, in a system where VDD is produced from VDDQ by a DC-DC converter, a heavy load is exerted on the VDDQ power supply, causing a phenomenon, in which the VDD power supply cannot be turned on. If the VDD power supply cannot be turned on, in0 and in0b remain undefined, leaving the system permanently unable to start normally.
Not only when the power is turned on, but while the VDDQ power supply is on, it is impossible to cut off the VDD power supply because the cutoff of the VDD power renders the values of in0 and in0b undefined, causing a through-current to flow through the VDDQ and resulting in a significant increase in power consumption by the system.
Furthermore, the conventional input/output circuit unit that includes an output buffer circuit unit also has a similar problem to that discussed above with respect to the level conversion circuit unit. When the VDDQ power supply is turned on but the VDD power is not, the input signal value of the output buffer of the input/output circuit becomes undefined, causing a through-current to flow between VDDQ and VSS of the output buffer circuit.
An object of this invention is to provide a level-down circuit that does not readily produce an erroneous output in the presence of ground level fluctuation in large-amplitude input signals, and to provide a semiconductor integrated circuit device employing the level-down circuit.
Another object of this invention is to provide a level conversion circuit in which no through-current flows between a high-voltage power supply and a ground power supply, and to provide a semiconductor integrated circuit device employing the level conversion circuit, even when the high-voltage power supply is turned on but the low-voltage power is not.
Another object of the present invention is to provide a semiconductor integrated circuit device including a plurality of circuit blocks powered by different respective supply voltage levels, and level conversion circuits according to the invention for translating voltage levels between the various circuit blocks.
To achieve these and other objects of the invention, and to solve problems of the prior art, the present invention includes one or more of the following features in the various embodiments discussed in greater detail below:
(1) The input to a level-down circuit is provided differentially;
(2) In the level-down circuit, MOS transistors that do not receive 3.3 V between gate and drain or between gate and source have thin gate oxide layers;
(3) A level-up circuit has a logical operation function; and
(4) An output buffer circuit provided with a level-up circuit includes means preventing a through-current from flowing through the output buffer when only one of the MOS transistors of the output buffer is turned on.